This invention relates to a semiconductor memory performing a write or read operation by decoding a row and a column address signal line.
FIG. 3 shows a conventional random access memory (RAM) such as shown in the 1985 Mitsubishi Semiconductor IC Memory Data Book published by Mitsubishi Denki. The RAM includes a memory cell array 1, a row address decoder 2, a column address decoder 3, a column selector circuit 4, a data output control signal line 5, and a data input control signal line 6, these devices being interconnected with each other as shown in the figure.
In operation, the row address decoder 2 decodes n input address signals and activates one of m row address signals and feeds it to the memory cell array 1. The column address decoder 3 decodes i input address signals and activates one of k column address signals and feeds it to the column selector circuit 4. The memory cell array 1 feeds the column selector circuit 4 with the data of b memory cells (not shown) sharing the common word line specified by the row address decoder 2. When the data output control signal line 5 is activated, the column selector circuit 4 selects the data specified by the column address decoder 3 from the b data and outputs it.
Where data is written in the memory cell array 1, the write position is specified in the same manner as described above and, then, the data input control signal line 6 is activated to allow data input from the outside.
FIG. 4 shows a conventional semiconductor read only memory (ROM). The ROM allows read only so that neither data output control signal line 5 nor data input control signal line 6 is provided and data is output from the column selector circuit 4.
As described above, neither conventional RAM nor ROM is able to read simultaneously a plurality of data of different addresses so that it takes a great amount of time to read a plurality of data.